cordic算法verilog实现（复杂版） - FPGA/ASIC技术 -
module cordic (clk,rst_n,ena,phase_in,sin_out,cos_out,eps);
parameter DATA_WIDTH=8;
parameter PIPELINE=8;
input clk;
input rst_n;
input ena;
input [DATA_WIDTH-1:0] phase_in;
output [DATA_WIDTH-1:0] sin_out;
output [DATA_WIDTH-1:0] cos_out;
output [DATA_WIDTH-1:0] eps;
reg [DATA_WIDTH-1:0] sin_out;
reg [DATA_WIDTH-1:0] cos_out;
reg [DATA_WIDTH-1:0] eps;
reg [DATA_WIDTH-1:0] phase_in_reg;
reg [DATA_WIDTH-1:0] x0,y0,z0;
reg [DATA_WIDTH-1:0] x1,y1,z1;
reg [DATA_WIDTH-1:0] x2,y2,z2;
reg [DATA_WIDTH-1:0] x3,y3,z3;
reg [DATA_WIDTH-1:0] x4,y4,z4;
reg [DATA_WIDTH-1:0] x5,y5,z5;
reg [DATA_WIDTH-1:0] x6,y6,z6;
reg [DATA_WIDTH-1:0] x7,y7,z7;
reg [1:0] quadrant[PIPELINE:0];
integer i;
//get real quadrant and map to first_n quadrant
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
phase_in_reg<=8'b0000_0000;
else
if(ena)
begin
case(phase_in[7:6])
2'b00:phase_in_reg<=phase_in;
2'b01:phase_in_reg<=phase_in-8'h40; //-pi/2
2'b10:phase_in_reg<=phase_in-8'h80; //-pi
2'b11:phase_in_reg<=phase_in-8'hc0; //-3pi/2
default:;
endcase
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x0<=8'b0000_0000;
y0<=8'b0000_0000;
z0<=8'b0000_0000;
end
else
if(ena)
begin
x0<=8'h4D; //define aggregate constant Xi=1/P=1/1.6467=0.60725 (Xi=2^7*P+8'h4D)
y0<=8'h00;
z0<=phase_in_reg;
end
end
//level 1
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x1<=8'b0000_0000;
y1<=8'b0000_0000;
z1<=8'b0000_0000;
end
else
if(ena)
if(z0[7]==1'b0)
begin
x1<=x0-y0;
y1<=y0+x0;
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