基于dsPIC33FJ设计的PSFB砖形DC-DC转换器技术 - 模拟电源 -

本文介绍了dsPIC33FJ系列主要特性，方框图和CPU 核方框图，DSP 引擎方框图，数字PFC框图以及多种应用框图。此外还介绍了相移全桥（PSFB） 1/4砖形DC-DC转换器参考设计主要特性和指标，详细电路图与材料清单（BOM）。

Microchip 公司的dsPIC33FJ06GS101/X02和dsPIC33FJ16GSX02/X04包括有广泛的DSP功能和高性能16位MCU架构。3.0-3.6V的性能达到40MIPS，具有16位宽的数据通路，24位宽指令，广泛应用在AC/DC转换器，汽车HID，电池充电器，DC/DC转换器，数字照明，电磁炉，可再生能源/纯正弦波逆变器和UPS。

dsPIC33FJ系列主要特性：

Operating Range:

Up to 40 MIPS Operation (at 3.0-3.6V):

- Industrial temperature range (-40℃ to +85℃)

- Extended temperature range (-40℃ to +125℃)

High-Performance DSC CPU:

Modified Harvard Architecture

C Compiler Optimized Instruction Set

16-Bit Wide Data Path

24-Bit Wide Instructions

Linear Program Memory Addressing up to 4M Instruction Words

Linear Data Memory Addressing up to 64 Kbytes

83 Base Instructions: Mostly 1 Word/1 Cycle

Two 40-Bit Accumulators with Rounding and Saturation Options

Flexible and Powerful Addressing modes:

- Indirect

- Modulo

- Bit-Reversed

Software Stack

16 x 16 Fractional/Integer Multiply Operations

32/16 and 16/16 Divide Operations

Single-Cycle Multiply and Accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

Up to ±16-Bit Shifts for up to 40-Bit Data

Digital I/

Peripheral Pin Select Functionality

Up to 35 Programmable Digital I/O Pins

Wake-up/Interrupt-on-Change for up to 30 Pins

Output Pins can Drive Voltage from 3.0V to 3.6V

Up to 5V Output with Open-Drain Configuration

5V Tolerant Digital Input Pins (except RB5)

16 mA Source/Sink on All PWM pins

On-Chip Flash and SRAM:

Flash Program Memory (up to 16 Kbytes)

Data SRAM (up to 2 Kbytes)

Boot and General Security for Program Flash

Peripheral Features:

Timer/Counters, up to Three 16-Bit Timers:

- Can pair up to make one 32-bit timer

Input Capture (up to two channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

Output Compare (up to two channels):

- Single or Dual 16-Bit Compare mode

- 16-Bit Glitchless PWM mode

4-Wire SPI:

- Framing supports I/O interface to simple codecs

- 1-deep FIFO Buffer.

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

I2C:

- Supports Full Multi-Master Slave mode

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

UART:

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

- IrDA encoding and decoding in hardware

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

Interrupt Controller:

5-Cycle Latency

Up to 35 Available Interrupt Sources

Up to Three External Interrupts

Seven Programmable Priority Levels

Four Processor Exceptions

High-Speed PWM Module Features:

Up to Four PWM Generators with Four to Eight Outputs

Individual Time Base and Duty Cycle for each of the Eight PWM Outputs

Dead Time for Rising and Falling Edges

Duty Cycle Resolution of 1.04 ns

Dead-Time Resolution of 1.04 ns

Phase Shift Resolution of 1.04 ns

Frequency Resolution of 1.04 ns

PWM modes Supported:

- Standard Edge-Aligned

- True Independent Output

- Complementary

- Center-Aligned

- Push-Pull

- Multi-Phase

- Variable Phase

- Fixed Off-Time

- Current Reset

- Current-Limit

Independent Fault/Current-Limit Inputs for 8 PWM Outputs

Output Override Control

Special Event Trigger

PWM Capture Feature

Prescaler for Input Clock

Dual Trigger from PWM to ADC

PWMxL, PWMxH Output Pin Swapping

PWM4H, PWM4L Pins Remappable

On-the-Fly PWM Frequency, Duty Cycle and Phase Shift Changes

Disabling of Individual PWM Generators

Leading-Edge Blanking (LEB) Functionality

High-Speed Analog Comparator

Up to Four Analog Comparators:

- 20 ns response time

- 10-bit DAC for each analog comparator

- DACOUT pin to provide DAC output

- Programmable output polarity

- Selectable input source

- ADC sample and convert capability

PWM Module Interface:

- PWM duty cycle control

- PWM period control

- PWM Fault detect

High-Speed 10-Bit ADC

10-Bit Resolution

Up to 12 Input Channels Grouped into Six Conversion Pairs

Two Internal Reference Monitoring Inputs Grouped into a Pair

Successive Approximation Register (SAR)

Converters for Parallel Conversions of Analog Pairs:

- 4 Msps for devices with two SARs

- 2 Msps for devices with one SAR

Dedicated Result Buffer for each Analog Channel

Independent Trigger Source Section for each Analog Input Conversion Pair

Power Management:

On-Chip 2.5V Voltage Regulator

Switch between Clock Sources in Real Time

Idle, Sleep, and Doze modes with Fast Wake-up

CMOS Flash Technology:

Low-Power, High-Speed Flash Technology

Fully Static Design

3.3V (±10%) Operating Voltage

Industrial and Extended Temperature

Low-Power Consumption

System Management:

Flexible Clock Options:

- External, crystal, resonator, internal RC

- Phase-Locked Loop (PLL) with 120 MHz VCO

- Primary Crystal Oscillator (OSC) in the range of 3 MHz to 40 MHz

- Internal Low-Power RC (LPRC) oscillator at a frequency of 32 kHz

- Internal Fast RC (FRC) oscillator at a frequency of 7.37 MHz

Power-on Reset (POR)

Brown-out Reset (BOR)

Power-up Timer (PWRT)

Oscillator Start-up Timer (OST)

Watchdog Timer with its RC Oscillator

Fail-Safe Clock Monitor (FSCM)

Reset by Multiple Sources

In-Circuit Serial Programming (ICSP)

Reference Oscillator Output

dsPIC33FJ 系列应用：

AC-to-DC Converters

Automotive HID

Battery Chargers

DC-to-DC Converters

Digital Lighting

Induction Cooking

LED Ballast

Renewable Power/Pure Sine Wave Inverters

Uninterruptible Power Supply (UPS)


图1。dsPIC33FJ06GS101/X02和dsPIC33FJ16GSX02/X04 方框图

图2。dsPIC33FJ06GS101/X02和dsPIC33FJ16GSX02/X04 CPU 核方框图

图3。DSP 引擎方框图

图4。dsPIC33FJ 数字PFC框图

图5。dsPIC33FJ 升压转换器框图

图6。dsPIC33FJ 单相同步降压转换器框图

图7。dsPIC33FJ 多相同步降压转换器框图

图8。dsPIC33FJ 离线UPS框图

图9。dsPIC33FJ 交叉PFC框图

图10。dsPIC33FJ 相移全桥（PSFB）转换器框图

图11。带PFC三输出(12V, 5V和3.3V)AC/DC电源框图

1/4砖形DC/DC转换器参考设计

Quarter Brick DC/DC Converter Reference Design

This reference design provides an easy method to evaluate the power, and features of SMPS dsPIC Digital Signal Controllers in high density quarter brick DC-DC converters for intermediate bus architectures(IBA). This reference design is implemented using a single dsPIC33F “GS” digital-power DSCs from Microchip that provides the full digital control of the power conversion and system management functions. As shown in this reference design the dsPIC33F ‘GS’ devices enable designers to easily and cost effectively create products using advanced switching techniques such as Phase Shift Full Bridge (PSFB) topology that lower switching losses and enable efficiencies as high as 94%. The Quarter brick DC/DC Converter Reference Design is royalty free when used in accordance with the licensing agreement.

This reference design works with telecom input range 36V – 76V DC and provides 12V with 200W power. Designed with planar magnetics, this reference design implements various non-linear techniques, which improves the performance and efficiency.

1/4砖形DC/DC转换器参考设计主要特性：

Primary and Secondary MOSFET control

Active Current Share

Remote ON/OFF

Programmable soft start

Controlled Fall time

Voltage,Current,Temperature monitoring & Protection

Configurable output voltage

Full Digital Control

1/4砖形DC/DC转换器参考设计指标：

Industry standard Quarter-brick (36.8 x 58.4 x 11.4 mm)

Wide input range 36V -76V

Output Voltage: 12V

Output Current: 17A

Output Power : 200W

Efficiency greater than 93%

1500 Vdc input to output isolation


图12。1/4砖形DC/DC转换器参考设计外形图

图13。1/4砖形DC/DC转换器的dsPIC DSC资源图

图14。PSFB 1/4砖形DC/DC转换器电路图（1）

图15。PSFB 1/4砖形DC/DC转换器电路图（2）

图16。PSFB 1/4砖形DC/DC转换器电路图（3）

图17。PSFB 1/4砖形DC/DC转换器电路图（4）

图18。基板电路图

　　　　　　　　　　　　　 查看评论 回复